2025-08-24: The circuit description eDSL in Scala: WireSynth.sc

🎉 Wiresynth is released and available in Maven Central! 🎉

I put it on hold for a really long time. lol

It took about 10 days since the project really started, until the first commit and publish to the Maven Central.

Now it’s able to elaborate designs and generate final netlist for KiCad Pcbnew editor. The syntax is partially following SpinalHDL.

I also wrote a script for migration from KiCad symbol and footprint files to Scala source files. This makes it ready for production.

WireSynth is intended to be a kit, not just a standalone eDSL. More tools will be available in the future.

2024-11-11: Designing one circuit description language for designing systems on PCB.

Inspired by register-level description language such as SystemVerilog. Dragging parts and wires on schematic in EDA is so boring and low-efficient. So I’m designing a description language for placing parts and wiring modules.

Reusing modules and layouts is also tough in KiCad and many EDAs. So it’s necessary to have one common layout format. Each module can have multiple layouts to choose.

Parameterization is useless just like the generate block in Verilog. The synthesizer itself could not provide enough flexibility and configurability.

Generating modules through Scala DSLs is a good idea. Inspired by Chisel and SpinalHDL.

PCB design is quite a bit different with FPGA. There is no logic, only parts and wires. Each bit in signal wire in Verilog is one single wire on PCB.

And PCB designer has to manually decide the positions and layout for the parts and wires. Looking for one approach to automate the layout is one of my motivations to learn Machine Learning.

I’ve got started with Julia language. But I still lack one GPGPU for discovering and practicing with the ML frameworks.