The circuit description eDSL in Scala: WireSynth.sc

🎉 Wiresynth is released and available in Maven Central! 🎉

I put it on hold for a really long time. lol

It took about 10 days since the project really started, until the first commit and publish to the Maven Central.

Now it's able to elaborate designs and generate final netlist for KiCad Pcbnew editor. The syntax is partially following SpinalHDL.

I also wrote a script for migration from KiCad symbol and footprint files to Scala source files. This makes it ready for production.

WireSynth is intended to be a kit, not just a standalone eDSL. More tools will be available in the future.

First encounter with dataflow architecture, and Manchester Prototype Dataflow Machine

On Jun 5th this year, I've thought that if we can analyze all the data dependence/relationship/path of the entire program, then we can execute the separated dataflows in parallel, and commit the result at the confluence node of the following dataflow. I named my implementation that have not done yet, called Paracell.

Recently I started learning about the dataflow architecture after the exploration about Interaction Net and HVM2. It was a research hotspot in 1970s and early 1980s. And the Wikipedia shown that my ideas were studied at that time.

In my thought, the main problems for application of theories are about the cost by synchronization, memory access, communication latency.